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Quad, 12-/14-/16-Bit nanoDACs(R) with 5 ppm/C On-Chip Reference AD5624R/AD5644R/AD5664R
FEATURES
Low power, smallest pin-compatible, quad nanoDACs AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/C reference 10-lead MSOP and 3 mm x 3 mm LFCSP_WD 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz
FUNCTIONAL BLOCK DIAGRAM
VDD GND VREFIN /VREFOUT 1.25V/2.5V REF
AD5624R/AD5644R/AD5664R
INPUT REGISTER SCLK INPUT REGISTER SYNC INTERFACE LOGIC INPUT REGISTER DIN INPUT REGISTER DAC REGISTER STRING DAC D DAC REGISTER STRING DAC C DAC REGISTER STRING DAC B DAC REGISTER STRING DAC A
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
Figure 1.
Table 1. Related Devices
Part No. AD5624/AD5664 AD5666 Description 2.7 V to 5.5 V quad,12-, 16-bit DACs, external reference 2.7 V to 5.5 V quad 16-bit DAC, internal reference, LDAC, CLR pins
APPLICATIONS
Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
GENERAL DESCRIPTION
The AD5624R/AD5644R/AD5664R, members of the nanoDAC family, are low power, quad, 12-, 14-, 16-bit buffered voltageout DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5624R/AD5644R/AD5664R have an on-chip reference. The AD56x4R-3 have a 1.25 V, 5 ppm/C reference, giving a full-scale output range of 2.5 V; the AD56x4R-5 have a 2.5 V, 5 ppm/C reference giving a full-scale output range of 5 V. The on-chip reference is off at power-up allowing the use of an external reference and all devices can be operated from a single 2.7 V to 5.5 V supply. The internal reference is enabled via a software write. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial interface that operates at clock rates up to 50 MHz, and is compatible with standard SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. Quad 12-, 14-, 16-bit DACs. On-chip 1.25 V/2.5 V, 5 ppm/C reference. Available in 10-lead MSOP and 10-lead, 3 mm x 3 mm, LFCSP_WD. Low power, typically consumes 1.32 mW at 3 V and 2.25 mW at 5 V.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05856-001
POWER-ON RESET
POWER-DOWN LOGIC
AD5624R/AD5644R/AD5664R TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AD5624R-5/AD5644R-5/AD5664R-5 ....................................... 3 AD5624R-3/AD5644R-3/AD5664R-3 ....................................... 5 AC Characteristics........................................................................ 6 Timing Characteristics ................................................................ 7 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 20 D/A Section................................................................................. 20 Resistor String ............................................................................. 20 Output Amplifier........................................................................ 20 Internal Reference ...................................................................... 20 External Reference...................................................................... 20 Serial Interface ............................................................................ 20 Input Shift Register .................................................................... 21 SYNC Interrupt .......................................................................... 21 Power-On Reset.......................................................................... 22 Software Reset............................................................................. 22 Power-Down Modes .................................................................. 22 LDAC Function........................................................................... 23 Internal Reference Setup ........................................................... 23 Microprocessor Interfacing....................................................... 24 Applications..................................................................................... 25 Using a Reference as a Power Supply for the AD5624R/AD5644R/AD5664R ............................................... 25 Bipolar Operation Using the AD5624R/AD5644R/AD5664R ....................................................................................................... 25 Using AD5624R/AD5644R/AD5664R with a Galvanically Isolated Interface ........................................................................ 25 Power Supply Bypassing and Grounding................................ 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 28
REVISION HISTORY
4/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5624R/AD5644R/AD5664R SPECIFICATIONS
AD5624R-5/AD5644R-5/AD5664R-5
VDD = 4.5 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE 2 AD5664R Resolution Relative Accuracy Differential Nonlinearity AD5644R Resolution Relative Accuracy Differential Nonlinearity AD5624R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Min B Grade 1 Typ Max Unit Conditions/Comments
16 8 16 1
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV mV % of FSR % of FSR V/C ppm dB V V/mA V V V/mA V
Guaranteed monotonic by design
14 2 4 0.5
Guaranteed monotonic by design
12 0.5 2 1 -0.1 2 2.5 -100 10 10 5 25 20 10 1 0.25 10 10 1 1.5
Guaranteed monotonic by design All zeroes loaded to DAC register All ones loaded to DAC register
Of FSR/C DAC code = midscale ; VDD = 5 V 10% Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel)
DC Crosstalk (Internal Reference)
OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage Reference TC3 Output Impedance
0 2 10 0.5 30 4 170 0.75 26 2.495 5 7.5
VDD
V nF nF mA s A V k V ppm/C k
RL = RL = 2 k VDD = 5 V Coming out of power-down mode; VDD = +5 V VREF = VDD = 5.5 V
200 VDD
2.505 10
At ambient
Rev. 0 | Page 3 of 28
AD5624R/AD5644R/AD5664R
Parameter LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) 5 VDD = 4.5 V to 5.5 V
1 2
Min
B Grade 1 Typ
Max 2 0.8
Unit A V V pF V mA mA A
Conditions/Comments All digital inputs VDD = 5 V VDD = 5 V
2 3 4.5 0.45 0.95 0.48 5.5 0.9 1.2 1
VIH = VDD, VIL = GND Internal reference off Internal reference on VIH = VDD, VIL = GND
Temperature range: B grade: -40C to +105C. Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down.
Rev. 0 | Page 4 of 28
AD5624R/AD5644R/AD5664R
AD5624R-3/AD5644R-3/AD5664R-3
VDD = 2.7 V to 3.6 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter STATIC PERFORMANCE2 AD5664R Resolution Relative Accuracy Differential Nonlinearity AD5644R Resolution Relative Accuracy Differential Nonlinearity AD5624R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Min B Grade1 Typ Max Unit Conditions/Comments
16 8 16 1
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV mV % of FSR % of FSR V/C ppm dB V V/mA V V V/mA V
Guaranteed monotonic by design
14 2 4 0.5
Guaranteed monotonic by design
12 0.5 2 1 -0.1 2 2.5 -100 10 10 5 25 20 10 1 0.25 10 10 1 1.5
Guaranteed monotonic by design All zeroes loaded to DAC register All ones loaded to DAC register
Of FSR/C DAC code = midscale; VDD = 3 V 10% Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel)
DC Crosstalk (Internal Reference)
OUTPUT CHARACTERISTICS3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage Reference TC3 Output Impedance
0 2 10 0.5 30 4 170 0 26 1.247 5 7.5
VDD
V nF nF mA s A V k V ppm/C k
RL = RL = 2 k VDD = 3 V Coming out of power-down mode; VDD = 3 V VREF = VDD = 3.6 V
200 VDD
1.253 15
At ambient
Rev. 0 | Page 5 of 28
AD5624R/AD5644R/AD5664R
Parameter LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 2.7 V to 3.6 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 3.6 V
1 2
Min
B Grade 1 Typ
Max 2 0.8
Unit A V V pF V mA mA A
Conditions/Comments All digital inputs VDD = 3 V VDD = 3 V
2 3 2.7 0.44 0.95 0.2 3.6 0.85 1.15 1
VIH = VDD, VIL = GND Internal reference off Internal reference on VIH = VDD, VIL = GND
Temperature range: B grade: -40C to +105C. Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4.
Parameter 2 Output Voltage Settling Time AD5624R AD5644R AD5664R Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise
1 2
Min
Typ 3 3.5 4 1.8 10 0.1 -90 0.1 1 4 1 4 340 -80 120 100 15
Max 4.5 5 7
Unit s s s V/s nV-s nV-s dBs nV-s nV-s nV-s nV-s nV-s kHz dB nV/Hz nV/Hz V p-p
Conditions/Comments 3 1/4 to 3/4 scale settling to 0.5 LSB 1/4 to 3/4 scale settling to 0.5 LSB 1/4 to 3/4 scale settling to 2 LSB 1 LSB change around major carry VREF = 2 V 0.1 V p-p, frequency 10 Hz to 20 MHz External reference Internal reference External reference Internal reference VREF = 2 V 0.1 V p-p VREF = 2 V 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 1 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz
Guaranteed by design and characterization, not production tested. See the Terminology section. 3 Temperature range is -40C to +105C, typical at 25C.
Rev. 0 | Page 6 of 28
AD5624R/AD5644R/AD5664R
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 5.
Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10
1 2
Limit at TMIN, TMAX VDD = 2.7 V to 5.5 V 20 9 9 13 5 5 0 15 13 0
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore
Guaranteed by design and characterization, not production tested. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t10
SCLK
t1
t9 t2
t8
SYNC
t4 t6
t3
t7
t5
DIN DB23
DB0
Figure 2. Serial Write Operation
Rev. 0 | Page 7 of 28
05856-002
AD5624R/AD5644R/AD5664R ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 6.
Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP_WD Package (4-Layer Board) JA Thermal Impedance MSOP Package (4-Layer Board) JA Thermal Impedance JC Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -65C to +150C 150C (TJ max - TA)/JA 61C/W 142C/W 43.7C/W 260C 5C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 28
AD5624R/AD5644R/AD5664R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUTA 1 VOUTB 2 GND 3 VOUTC 4 VOUTD 5
AD5624R/ AD5644R/ AD5664R
TOP VIEW (Not to Scale)
10 VREFIN /VREFOUT 9 8 7 6
VDD DIN SYNC
05856-003
SCLK
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic VOUTA VOUTB GND VOUTC VOUTD SYNC Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground Reference Point for all Circuitry on the Part. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input.
7 8 9 10
SCLK DIN VDD VREFIN/VREFOUT
Rev. 0 | Page 9 of 28
AD5624R/AD5644R/AD5664R TYPICAL PERFORMANCE CHARACTERISTICS
4 3 2 1 0 -1 -2
05856-005
VDD = VREF = 5V TA = 25C
1.0 0.8 0.6
DNL ERROR (LSB)
VDD = VREF = 5V TA = 25C
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 10k 20k 30k CODE 40k 50k 60k
05856-007
INL ERROR (LSB)
-3 -4
0
2500
5000
7500 10000 CODE
12500
15000
Figure 4. INL AD5664R, External Reference
4 3 2 1 0 -1 -2
-0.3
05856-005
Figure 7. DNL AD5664R, External Reference
0.5 0.4 0.3
DNL ERROR (LSB)
VDD = VREF = 5V TA = 25C
VDD = VREF = 5V TA = 25C
0.2 0.1 0 -0.1 -0.2
INL ERROR (LSB)
-0.4 -0.5 0 2500 5000 7500 10000 CODE 12500 15000
-4
0
2500
5000
7500 10000 CODE
12500
15000
Figure 5. INL AD5644R, External Reference
1.0 VDD = VREF = 5V 0.8 TA = 25C 0.6
DNL ERROR (LSB)
Figure 8. DNL AD5644R, External Reference
0.20 0.15 0.10 0.05 0 -0.05 -0.10
05856-009
VDD = VREF = 5V TA = 25C
0.4
INL ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
05856-006
-0.15 -0.20
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
Figure 6. INL AD5624R, External Reference
Figure 9. DNL AD5624R, External Reference
Rev. 0 | Page 10 of 28
05856-008
-3
AD5624R/AD5644R/AD5664R
10 8 6
INL ERROR (LSB)
1.0
VDD = 5V VREFOUT = 2.5V TA = 25C
0.8 0.6
DNL ERROR (LSB)
VDD = 5V VREFOUT = 2.5V TA = 25C
4 2 0 -2 -4 -6 -8 -10
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000
05856-010
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000
05856-013
CODE
CODE
Figure 10. INL AD5664R-5, Internal Reference
4 3 2 1 0 -1 -2
-0.3 -0.4 -0.5 0.5
Figure 13. DNL AD5664R-5, Internal Reference
VDD = 5V VREFOUT = 2.5V TA = 25C
VDD = 5V VREFOUT = 2.5V TA = 25C
0.4 0.3
DNL ERROR (LSB)
INL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2
0
0
-4
1250 2500 3750 5000 6250 7500 8750 10000 11250 12500 13750 15000 16250
05856-011
1250
2500
3750
5000
6250
7500
8750
10000
11250
12500
13750
15000
CODE
CODE
Figure 11. INL AD5644R-5, Internal Reference
1.0 0.8 0.6
INL ERROR (LSB)
Figure 14. DNL AD5644R-5, Internal Reference
0.20 VDD = 5V VREFOUT = 2.5V TA = 25C
VDD = 5V VREFOUT = 2.5V TA = 25C
0.15 0.10
DNL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
05856-012
0.05 0 -0.05 -0.10
05856-015
-0.15 -0.20
0
500
1000
1500
2000 2500 CODE
3000
3500
4000
Figure 12. INL AD5624R-5, Internal Reference
Figure 15. DNL AD5624R-5, Internal Reference
Rev. 0 | Page 11 of 28
16250
05856-014
-3
AD5624R/AD5644R/AD5664R
10 8 6
INL ERROR (LSB)
1.0 VDD = 3V VREFOUT = 1.25V TA = 25C 0.8 0.6
DNL ERROR (LSB)
VDD = 3V VREFOUT = 1.25V TA = 25C
4 2 0 -2 -4 -6 -8 -10
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000
05856-016
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 55000 60000 65000 16250
05856-019 05856-021 05856-020
CODE
CODE
Figure 16. INL AD5664R-3, Internal Reference
4 3 2 1 0 -1 -2 -0.3
05856-017
Figure 19. DNL AD5664R-3, Internal Reference
0.5 VDD = 3V VREFOUT = 1.25V TA = 25C
VDD = 3V VREFOUT = 1.25V TA = 25C
0.4 0.3
DNL ERROR (LSB)
INL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2
-3 -4
0 11250 1250 2500 3750 5000 6250 7500 8750 10000 12500 13750 15000 16250
-0.4 -0.5
0 10000 11250 1250 2500 3750 5000 6250 7500 8750 12500 13750 15000
CODE
CODE
Figure 17. INL AD5644R-3, Internal Reference
1.0 0.8 0.6
INL ERROR (LSB)
Figure 20. DNL AD5644R-3, Internal Reference
0.20 VDD = 3V VREFOUT = 1.25V TA = 25C
VDD = 3V VREFOUT = 1.25V TA = 25C
0.15 0.10
DNL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
05856-018
0.05 0 -0.05 -0.10 -0.15 -0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 4000
-1.0
Figure 18. INL AD5624R-3, Internal Reference
Figure 21. DNL AD5624R-3, Internal Reference
Rev. 0 | Page 12 of 28
AD5624R/AD5644R/AD5664R
8 6 VDD = VREF = 5V 4
-0.06 0
MAX INL
-0.02 -0.04
VDD = 5V
GAIN ERROR
ERROR (LSB)
2 MAX DNL 0 -2 -4 MIN INL
05856-022
ERROR (% FSR)
-0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -20 0 20 40 60 TEMPERATURE (C) 80 100
05856-025 05856-027 05856-026
MIN DNL
FULL-SCALE ERROR
-6 -8 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
-0.20 -40
Figure 22. INL Error and DNL Error vs. Temperature
10 8 6 4
ERROR (LSB)
Figure 25. Gain Error and Full-Scale Error vs. Temperature
1.5
MAX INL
1.0 0.5
ZERO-SCALE ERROR
VDD = 5V TA = 25C MAX DNL
ERROR (mV)
2 0 -2 -4 MIN DNL
0 -0.5 -1.0 -1.5
-6 -8 -10 0.75 1.25 1.75 2.25 2.75 3.25 VREF (V) 3.75 MIN INL
-2.0
05856-023
OFFSET ERROR
4.25
4.75
-2.5 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 23. INL and DNL Error vs. VREF
8 6 TA = 25C 4 MAX INL
Figure 26. Zero-Scale Error and Offset Error vs. Temperature
1.0
0.5 GAIN ERROR
ERROR (LSB)
2 MAX DNL 0 -2 -4 MIN INL -6
05856-024
ERROR (% FSR)
0 FULL-SCALE ERROR -0.5
MIN DNL
-1.0
-1.5
-8 2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2
-2.0 2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2
Figure 24. INL and DNL Error vs. Supply
Figure 27. Gain Error and Full-Scale Error vs. Supply
Rev. 0 | Page 13 of 28
AD5624R/AD5644R/AD5664R
1.0 TA = 25C 0.5 0 ZERO-SCALE ERROR
8 7 6 VDD = 3.6V TA = 25C
FREQUENCY
ERROR (mV)
5 4 3 2
-0.5 -1.0 -1.5 -2.0 -2.5 2.7
OFFSET ERROR
05856-028
0
3.2
3.7
4.2 VDD (V)
4.7
5.2
0.39
0.40
0.41 IDD (mA)
0.42
0.43
Figure 28. Zero-Scale Error and Offset Error vs. Supply
6 5 VDD = 5.5V TA = 25C
Figure 31. IDD Histogram with External Reference, 3.6 V
8 7 6 VDD = 3.6V TA = 25C
FREQUENCY
FREQUENCY
4
5 4 3 2
3 2
05856-029
0
0.41
0.42
0.43 IDD (mA)
0.44
0.45
0
0.90
0.92
0.94 IDD (mA)
0.96
Figure 29. IDD Histogram with External Reference, 5.5 V
6 VDD = 5.5V TA = 25C
Figure 32. IDD Histogram with Internal Reference, VREFOUT = 1.25 V
0.5 0.4 0.3 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT
5
FREQUENCY
4
ERROR VOLTAGE (V)
0.2 0.1 0 -0.1 -0.2 -0.3 VDD = 5V VREFOUT = 2.5V VDD = 3V VREFOUT = 1.25V
3
2
1
05856-030
-0.4 -8 -6 -4 -2 0 2 CURRENT (mA) 4 6 8 10
05856-031
0
0.92
0.94
0.96 IDD (mA)
0.98
-0.5 -10
Figure 30. IDD Histogram with Internal Reference, VREFOUT = 2.5 V
Figure 33. Headroom at Rails vs. Source and Sink
Rev. 0 | Page 14 of 28
05856-061
1
1
05856-060
1
AD5624R/AD5644R/AD5664R
6 5 4 3 2 1/4 SCALE 1 VDD = 5V VREFOUT = 2.5V TA = 25C FULL SCALE
3/4 SCALE
MIDSCALE
VDD = VREF = 5V TA = 25C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2k AND 200pF TO GND
VOUT (V)
VOUT = 909mV/DIV
0 -1 -30 ZERO SCALE
05856-046
1
05856-048
-20
-10
0 10 CURRENT (mA)
20
30
TIME BASE = 4s/DIV
Figure 34. AD56x4R-5 Source and Sink Capability
4 VDD = 3V VREFOUT = 1.25V TA = 25C FULL SCALE 3/4 SCALE MIDSCALE 1 1/4 SCALE
Figure 37. Full-Scale Settling Time, 5 V
VDD = VREF = 5V TA = 25C
3
VOUT (V)
2
VDD 1
0
ZERO SCALE
2 VOUT
05856-047
MAX(C2) 420.0mV
-1 -30
-20
-10
0 10 CURRENT (mA)
20
30
CH1 2.0V
CH2 500mV
M100s 125MS/s A CH1 1.28V
8.0ns/pt
Figure 35. AD56x4R-3 Source and Sink Capability
0.50 0.45 0.40 0.35
1
Figure 38. Power-On Reset to 0 V
SYNC
VDD = VREFIN = 5V
VDD = VREFIN = 3V
3
SLCK
IDD (mA)
0.30 0.25 0.20 0.15 0.10 0.05
05856-063
VOUT 2
VDD = 5V
05856-050
TA = 25C 0 -40 -20
0
20 40 60 TEMPERATURE (C)
80
100
CH1 5.0V CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
Figure 36. Supply Current vs. Temperature
Figure 39. Exiting Power-Down to Midscale
Rev. 0 | Page 15 of 28
05856-049
AD5624R/AD5644R/AD5664R
2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 VDD = VREF = 5V TA = 25C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF)
VDD = VREF = 5V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
1
0
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
512
05856-058
Y AXIS = 2V/DIV X AXIS = 4s/DIV
Figure 40. Digital-to-Analog Glitch Impulse (Negative)
2.498 2.497 2.496 2.495 2.494 2.493 2.492 2.491 VDD = VREF = 5V TA = 25C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
VDD = 5V VREFOUT = 2.5V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
10V/DIV
1
05856-059
0
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
512
5s/DIV
Figure 41. Analog Crosstalk, External Reference
2.496 2.494 2.492 2.490 2.488 2.486 2.484 2.482 2.480 2.478 2.476 2.474 2.472 2.470 2.468 2.466 2.464 2.462 2.460 2.458 2.456
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
VDD = 3V VREFOUT = 1.25V TA = 25C DAC LOADED WITH MIDSCALE
VOUT (V)
5V/DIV
1
05856-062
0
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
512
4s/DIV
Figure 42. Analog Crosstalk, Internal Reference
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference
Rev. 0 | Page 16 of 28
05856-053
VDD = 5V VREFOUT = 2.5V TA = 25C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 4.462nV
05856-052
05856-051
AD5624R/AD5644R/AD5664R
800 700 TA = 25C MIDSCALE LOADED 16 VREF = VDD TA = 25C 14
OUTPUT NOISE (nV/Hz)
600 500 400 300 200 100 0 100 VDD = 3V VREFOUT = 1.25V
05856-054
VDD = 3V 12
TIME (s)
10
VDD = 5V VREFOUT = 2.5V
8
VDD = 5V
6
1k
10k FREQUENCY (Hz)
100k
1M
0
1
2
3
4 5 6 7 CAPACITANCE (nF)
8
9
10
Figure 46. Noise Spectral Density, Internal Reference
-20 -30 -40 -50 VDD = 5V TA = 25C DAC LOADED WITH FULL SCALE VREF = 2V 0.3V p-p 5 0 -5 -10
Figure 48. Settling Time vs. Capacitive Load
VDD = 5V TA = 25C
(dB)
-60 -70 -80 -90
05856-055
(dB)
-15 -20 -25 -30 -35
2k
4k 6k FREQUENCY (Hz)
8k
10k
100k 1M FREQUENCY (Hz)
10M
Figure 47. Total Harmonic Distortion
Figure 49. Multiplying Bandwidth
Rev. 0 | Page 17 of 28
05856-057
-100
-40 10k
05856-056
4
AD5624R/AD5644R/AD5664R TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 7. Zero-Scale Error Zero-scale error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5664R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 26. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 25. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as % of FSR. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5664R with code 512 loaded in the DAC register. It can be negative or
positive.
Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 40). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. A plot of noise spectral density can be seen in Figure 46. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in V. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in V/mA. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s.
DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by 10%.
Rev. 0 | Page 18 of 28
AD5624R/AD5644R/AD5664R
Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB.
Rev. 0 | Page 19 of 28
AD5624R/AD5644R/AD5664R THEORY OF OPERATION
D/A SECTION
The AD5624R/AD5644R/AD5664R DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 50 shows a block diagram of the DAC architecture.
VDD REF (+) DAC REGISTER RESISTOR STRING REF (-) OUTPUT AMPLIFIER (GAIN = +2) VOUT
R
R
R
TO OUTPUT AMPLIFIER
05856-032
R
GND
Figure 50. DAC Architecture
R
05856-033
Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by
Figure 51. Resistor String
VOUT = VREFIN
D x N 2
INTERNAL REFERENCE
The AD5624R/AD5644R/AD5664R on-chip reference is off at power-up and is enabled via a write to a control register. See the Internal Reference Setup section for details. The AD56x4R-3 has a 1.25 V, 5 ppm/C reference giving a fullscale output of 2.5 V. The AD56x4R-5 has a 2.5 V, 5 ppm/C reference giving a full-scale output of 5 V. The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor is placed between reference output and GND for reference stability.
The ideal output voltage when using the internal reference is given by D VOUT = 2 x V REFOUT x N 2 where: D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 4095 for AD5624R (12 bit). 0 to 16,383 for AD5644R (14 bit). 0 to 65,535 for AD5664R (16 bit). N is the DAC resolution.
EXTERNAL REFERENCE
The VREFIN pin on the AD56x4R-3 and AD56x4R-5 allows the use of an external reference if the application requires it. The default condition of the on-chip reference is off at power-up. All devices (AD56x4R-3 and the AD56x4R-5) can be operated from a single 2.7 V to 5.5 V supply.
RESISTOR STRING
The resistor string is shown in Figure 51. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
SERIAL INTERFACE
The AD5624R/AD5644R/AD5664R have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5624R/AD5644R/AD5664R compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 32 and Figure 33. The slew rate is 1.8 V/s with a 1/4 to 3/4 full-scale settling time of 7 s.
Rev. 0 | Page 20 of 28
AD5624R/AD5644R/AD5664R
At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As mentioned previously, it must, however, be brought high again just before the next write sequence.
Table 8. Command Definition
C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 Command Write to input register n Update DAC register n Write to input register n, update all (software LDAC) Write to and update DAC channel n Power down DAC (power-up) Reset LDAC register setup Internal reference setup (on/off )
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 52). The first two bits are don't care bits. The next three are the command bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address, A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word. The data-word comprises the 16-, 14-, 12-bit input code followed by 0, 2, or 4 don't care bits, for the AD5664R, AD5644R, and AD5624R, respectively (see Figure 52, Figure 53, and Figure 54). These data bits are transferred to the DAC register on the 24th falling edge of SCLK.
Table 9. Address Command
A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 ADDRESS (n) DAC A DAC B DAC C DAC D All DACs
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, then this acts as an interrupt to the write sequence. The input shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 55).
DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
DB0 (LSB) D1 D0
05856-034
DATA BITS COMMAND BITS ADDRESS BITS
Figure 52. AD5664R Input Shift Register Contents
DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB0 (LSB) X X
05856-035
DATA BITS COMMAND BITS ADDRESS BITS
Figure 53. AD5644R Input Shift Register Contents
DB23 (MSB) X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DB0 (LSB) X X
05856-036
DATA BITS COMMAND BITS ADDRESS BITS
Figure 54. AD5624R Input Shift Register Contents
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
05856-037
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE
Figure 55. SYNC Interrupt Facility
Rev. 0 | Page 21 of 28
AD5624R/AD5644R/AD5664R
POWER-ON RESET
The AD5624R/AD5644R/AD5664R family contains a power-on reset circuit that controls the output voltage during power-up. The AD5624R/AD5644R/AD5664R DACs output power up to 0 V and the output remains there until a valid write sequence is made to the DACs. This is useful in applications where it is important to know the state of the output of the DACs while they are in the process of powering up. By executing the same Command 100, any combination of DACs can be powered up by setting the bits (DB5 and DB4) to normal operation mode. To select which combination of DAC channels to power-up, set the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. See Table 13 for contents of the input shift register during power-down/power-up operation.
Table 11. Modes of Operation for the AD5624R/AD5644R/ AD5664R
DB5 0 0 1 1 DB4 0 1 0 1 Operating Mode Normal operation Power-down modes 1 k to GND 100 k to GND Three-state
SOFTWARE RESET
The AD5624R/AD5644R/AD5664R contain a software reset function. Command 101 is reserved for the software reset function (see Table 8). The software reset command contains two reset modes that are software programmable by setting bit DB0 in the control register. Table 10 shows how the state of the bit corresponds to the software reset modes of operation of the devices. Table 12 shows the contents of the input shift register during the software reset mode of operation.
Table 10. Software Reset Modes for the AD5624R/AD5644R/AD5664R
DB0 0 1 (Power-On Reset) Registers Reset to Zero DAC register Input shift register DAC register Input shift register LDAC register Power-down register Internal reference setup register
When Bit DB5 and Bit DB4 are set to 0, the part works normally with its normal power consumption of 450 A at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This allows the output impedance of the part to be known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 k resistor, or left open-circuited (three-state) as shown in Figure 54.
RESISTOR STRING DAC
AMPLIFIER
VOUT
The AD5624R/AD5644R/AD5664R contain four separate modes of operation. Command 100 is reserved for the power-down function (see Table 8). These modes are software programmable by setting two bits (DB5 and DB4) in the control register. Table 11 shows how the state of the bits corresponds to the mode of operation of the device. All DACs, (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB3, DB2, DB1, and DB0) to 1.
DB23 to DB22 (MSB) x Don't care
Figure 56. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shutdown when powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 s for VDD = 5 V and for VDD = 3 V (see Figure 39). Table 12. 24-Bit Input Shift Register Contents for Software Reset Command
DB21 DB20 DB19 1 0 1 Command bits (C2 to C0) DB18 DB17 DB16 x x x Address bits (A2 to A0) DB15 to DB1 x Don't care DB0 (LSB) 1/0 Determines software reset mode
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for the AD5624R/AD5644R/AD5664R
DB23 to DB22 (MSB) x Don't care DB15 to DB6 x Don't care DB0 (LSB) DAC A
DB21 1
DB20 0
DB19 0
DB18 x
DB17 x
DB16 x
DB5 PD1
DB4 PD0
DB3 DAC D
DB2 DAC C
DB1 DAC B
Command bits (C2 to C0)
Address bits (A2 to A0) Don't care
Power-down mode
Power-down/power-up channel selection, set bit to 1 to select channel
Rev. 0 | Page 22 of 28
05856-038
POWER-DOWN MODES
POWER-DOWN CIRCUITRY
RESISTOR NETWORK
AD5624R/AD5644R/AD5664R
LDAC FUNCTION
The AD5624R/AD5644R/AD5664R DACs have doublebuffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then write to the remaining input register, updating all DAC registers simultaneously. Command 010 is reserved for this software LDAC. Access to the DAC registers is controlled by the LDAC function. The LDAC register contains two modes of operation for each DAC channel. The DAC channels are selected by setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and DB0). Command 110 is reserved for setting up the LDAC register. When the LDAC bit register is set low, the corresponding DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. When the LDAC bit register is set high, however, the DAC registers become transparent and the contents of the input registers are transferred to them on the falling edge of the 24th SCLK pulse. This is equivalent to having an LDAC hardware pin tied permanently low for the selected DAC channel, that is, synchronous update mode. See Table 14 for the LDAC register mode of operation. See Table 16 for contents of the input shift register during the LDAC register setup command.
DB23 to DB22 (MSB) x
This flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the channels update synchronously.
Table 14. LDAC Register Mode of Operation
Load DAC Register LDAC Bits (DB3 to DB0) 0 1
LDAC Mode of Operation Normal operation (default), DAC register update is controlled by write command. The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse.
INTERNAL REFERENCE SETUP
The on-chip reference is off at power-up by default. This reference can be turned on or off by setting a software programmable bit, DB0 in the control register. Table 15 shows how the state of the bit corresponds to the mode of operation. Command 111 is reserved for setting up the internal reference (see Table 2). Table 16 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup.
Table 15. Reference Set-up Register
Internal Reference Setup Register (DB0) 0 1 Action Reference off (default) Reference on
Table 16. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624R/AD5644R/AD5664R
DB21
1
DB20
1
DB19
0
DB18
x
DB17
x
DB16
x
DB15 to DB4 x
DB3 DAC D
DB2 DAC C
DB1 DAC B
DB0 (LSB) DAC A
Don't care
Command bits (C2 to C0)
Address bits (A2 to A0); don't care
Don't care
Set bit to 0 or 1 for required mode of operation on respective channel
Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command
DB23 to DB22 (MSB) x Don't care DB21 DB20 DB19 1 1 1 Command bits (C2 to C0) DB18 DB17 DB16 x x x Address bits (A2 to A0) DB15 to DB1 x Don't care DB0 (LSB) 1/0 Reference setup register
Rev. 0 | Page 23 of 28
AD5624R/AD5644R/AD5664R
MICROPROCESSOR INTERFACING
AD5624R/AD5644R/AD5664R to Blackfin(R) ADSP-BF53x Interface
Figure 57 shows a serial interface between the AD5624R/ AD5644R/AD5664R and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5624R/AD5644R/AD5664R, the setup for the interface is that the DT0PRI drives the DIN pin of the AD5624R/ AD5644R/AD5664R, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0.
ADSP-BF53x1
AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface
Figure 59 shows a serial interface between the AD5624R/ AD5644R/AD5664R and the 80C51/80L51 microcontroller. The setup for the interface is that the TxD of the 80C51/80L51 drives SCLK of the AD5624R/AD5644R/AD5664R, while RxD drives the serial data line of the part. The SYNC signal is derived from a bitprogrammable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5624R/AD5644R/AD5664R, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in LSB first format. The AD5624R/ AD5644R/AD5664R must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account.
80C51/80L511
AD5624R/ AD5644R/ AD5664R1
SYNC DIN
05856-039
TFS0 DTOPRI TSCLK0
SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD5624R/ AD5644R/ AD5664R1
SYNC SCLK
05856-041 05856-042
Figure 57. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD5664R
P3.3 TxD RxD
1ADDITIONAL
AD5624R/AD5644R/AD5664R to 68HC11/68L11 Interface
Figure 58 shows a serial interface between the AD5624R/ AD5644R/AD5664R and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/ AD5644R/AD5664R, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are that the 68HC11/68L11 is configured with its CPOL bit as 0 and its CPHA bit as 1. When data is transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5624R/AD5644R/AD5664R, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure.
68HC11/68L111
DIN
PINS OMITTED FOR CLARITY.
Figure 59. 80C51/80L51 Interface to AD5624R/AD5644R/AD5664R
AD5624R/AD5644R/AD5664R to MICROWIRE Interface
Figure 60 shows an interface between the AD5624R/AD5644R/ AD5664R and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5624R/AD5644R/AD5664R on the rising edge of the SK.
MICROWIRE1
AD5624R/ AD5644R/ AD5664R1
SYNC SCLK DIN
CS SK SO
1ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 60. MICROWIRE Interface to AD5624R/AD5644R/AD5664R
AD5624R/ AD5644R/ AD5664R1
SYNC SCLK
05856-040
PC7 SCK MOSI
1ADDITIONAL
DIN
PINS OMITTED FOR CLARITY.
Figure 58. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R
Rev. 0 | Page 24 of 28
AD5624R/AD5644R/AD5664R APPLICATIONS
USING A REFERENCE AS A POWER SUPPLY FOR THE AD5624R/AD5644R/AD5664R
Because the supply current required by the AD5624R/AD5644R/ AD5664R is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 61). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5624R/AD5644R/ AD5664R (see Figure 59). If the low dropout REF195 is used, it must supply 450 A of current to the AD5624R/AD5644R/ AD5664R with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 k load on the DAC output) is 450 A + (5 V/5 k) = 1.45 mA The load regulation of the REF195 is typically 2 ppm/mA, resulting in a 2.9 ppm (14.5 V) error for the 1.45 mA current drawn from it. This corresponds to a 0.191 LSB error.
15V REF195 5V
This is an output voltage range of 5 V, with 0x0000 corresponding to a -5 V output, and 0xFFFF corresponding to a +5 V output.
R2 = 10k +5V +5V R1 = 10k
AD820/ OP295
VDD 10F 0.1F VOUT -5V
5V
AD5624R/ AD5644R/ AD5664R
Figure 62. Bipolar Operation with the AD5624R/AD5644R/AD5664R
USING AD5624R/AD5644R/AD5664R WITH A GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5624R/AD5644R/AD5664R use a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolator provides the required isolation (see Figure 63). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5624R/ AD5644R/AD5664R.
5V REGULATOR POWER 10F 0.1F
3-WIRE SERIAL INTERFACE
SYNC SCLK DIN
VDD
AD5624R/ AD5644R/ AD5664R
VOUT = 0V TO 5V
Figure 61. REF195 as Power Supply to the AD5624R/AD5644R/AD5664R
BIPOLAR OPERATION USING THE AD5624R/AD5644R/AD5664R
The AD5624R/AD5644R/AD5664R has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 62. The circuit gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
D R1 + R2 R2 VO = VDD x x - VDD x R1 65,536 R1
05856-043
SCLK
V1A
VOA
SCLK
VDD
ADuM1300
SDI V1B VOB SYNC VOUT
DATA
V1C
VOC
DIN
AD5624R/ AD5644R/ AD5664R
05856-045
GND
Figure 63. AD5624R/AD5644R/AD5664R with a Galvanically Isolated Interface
where D represents the input code in decimal (0 to 65536). With VDD = 5 V, R1 = R2 = 10 k,
10 x D VO = -5 V 65,536
Rev. 0 | Page 25 of 28
05856-044
3-WIRE SERIAL INTERFACE
AD5624R/AD5644R/AD5664R
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5624R/ AD5644R/AD5664R should have separate analog and digital sections, each having its own area of the board. If the AD5624R/ AD5644R/AD5664R are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5624R/AD5644R/AD5664R. The power supply to the AD5624R/AD5644R/AD5664R should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be located as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitor is the tantalum bead type. It is important that the 0.1 F capacitor have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
Rev. 0 | Page 26 of 28
AD5624R/AD5644R/AD5664R OUTLINE DIMENSIONS
INDEX AREA
3.00 BSC SQ
10
PIN 1 INDICATOR
1
1.50 BCS SQ
TOP VIEW
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
2.48 2.38 2.23
5
6
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 TYP
SIDE VIEW
0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF
1.74 1.64 1.49
0.30 0.23 0.18
Figure 64. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40
10 6
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
Figure 65. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
Rev. 0 | Page 27 of 28
AD5624R/AD5644R/AD5664R
ORDERING GUIDE
Model AD5624RBCPZ-3250R7 1 AD5624RBCPZ-3REEL71 AD5624RBRMZ-31 AD5624RBRMZ-3REEL71 AD5624RBRMZ-51 AD5624RBRMZ-5REEL71 AD5644RBRMZ-31 AD5644RBRMZ-3REEL71 AD5644RBRMZ-51 AD5644RBRMZ-5REEL71 AD5664RBCPZ-3250R71 AD5664RBCPZ-3REEL71 AD5664RBRMZ-31 AD5664RBRMZ-3REEL71 AD5664RBRMZ-51 AD5664RBRMZ-5REEL71 EVAL-AD5664REB
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Accuracy 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL
Internal Reference 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V
Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board
Package Option CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10
Branding D7L D7L D7L D7L D7V D7V D7E D7E D7D D7D D73 D73 D73 D73 D75 D75
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05856-0-4/06(0)
Rev. 0 | Page 28 of 28

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